Download Design of Integrated Circuits for Optical Communications by Behzad Razavi PDF
By Behzad Razavi
The purely ebook on built-in circuits for optical communications that totally covers High-Speed IOs, PLLs, CDRs, and transceiver layout together with optical communication
The expanding call for for high-speed delivery of knowledge has revitalized optical communications, resulting in huge paintings on high-speed machine and circuit layout. With the proliferation of the web and the increase within the pace of microprocessors and stories, the delivery of information is still the bottleneck, motivating paintings on swifter conversation channels.
Design of built-in Circuits for Optical Communications, moment version deals with the layout of high-speed built-in circuits for optical conversation transceivers.
Building upon an in depth knowing of optical units, the e-book describes the research and layout of serious development blocks, equivalent to transimpedance and proscribing amplifiers, laser drivers, phase-locked loops, oscillators, clock and knowledge restoration circuits, and multiplexers.
The Second Edition of this bestselling textbook has been absolutely up-to-date with:
- A educational therapy of broadband circuits for either scholars and engineers
- New and distinctive details facing clock and knowledge restoration circuits and multiplexers
- A bankruptcy devoted to burst-mode optical communications
- A special examine of latest circuit advancements for optical transceivers
- An exam of modern implementations in CMOS technology
This textual content is perfect for senior graduate scholars and engineers considering high-speed circuit layout for optical communications, in addition to the extra normal box of wireline communications.
Read Online or Download Design of Integrated Circuits for Optical Communications PDF
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Additional resources for Design of Integrated Circuits for Optical Communications
For example, consider the simple structure shown in Fig. 28(a), where an ideal interconnect (with zero resistance) and a ground plane form a T line. A step applied to one end experiences delay as it propagates through the line. As depicted in Fig. 28(b), the line can be modeled by a distributed LC ladder, where LQ and Co denote the inductance and capacitance of the line per unit length, respectively. The delay is calculated from the velocity of the wave, given by V =^=F^- (2-40) Note that the propagation behavior and the delay in this case are quite different from those of long on-chip interconnects exhibiting substantial series resistance.
As a result, the bits after each long run suffer from a large (temporary) dc shift, making it difficult to set a decision threshold. This phenomenon can also be viewed as ISI because each bit level depends on the preceding pattern. The above effect is called "dc wander" (or "baseline wander") because the "instantaneous" dc value of the output waveform continues to change randomly. To minimize dc wander, T\ = Ri C\ must be sufficiently greater than the longest permissible run to ensure negligible droop.
For example, if the threshold is set at V¡)/2, then the levels at t — t\, and t — ¿2 are very susceptible to noise and can be misinterpreted by the detector. Also, the time instants at which the waveform crosses Vb/2 experience random variations. The above phenomenon is called "intersymbol interference" (ISI) because it can also be viewed as follows. Suppose, as shown in Fig. 12(a), the input data sequence is represented by a superposition of positive and negative steps. Each step gives rise to an exponential response at the output [Fig.