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Additional info for CompactPCI specification short form Rev 2.1
It has a fixed size F due to the fixed number of accumulator bits built into the hardware. The dual-modulus prescaler ratio P is normally fixed as well. 2 is the accumulator input K, which can be programmed from one to a maximum number of F. 6) where R is normally fixed to avoid changing the comparison frequency at the input. Note that R is normally as small as possible to minimize the in-band phase noise contribution from the crystal. Thus, step size is inversely proportional to the number of bits (log 2 F); as a result, the accumulator is normally used to reduce synthesizer step size without increasing R and degrading the in-band phase noise.
The summing block in the feedback is commonly called a phase detector. Through feedback, the loop forces the phase of the signal source to track the phase of the feedback signal; therefore, their frequencies must be equal. 1) Due to divider implementation details, it is not easy to make a divider that divides by noninteger values. Thus, a PLL synthesizer of this type is called an integer-N frequency synthesizer. Circuits inside the feedback loop can be described by their transfer functions. These transfer functions can be designed to engineer the system dynamics to meet design specifications for the synthesizer.
Samueli, ‘‘An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation,’’ Proc. , Philadelphia, PA, May 1987, pp. 495–502. , and F. Maloberti, ‘‘A Direct-Digital Synthesizer with Improved Spectral Performance,’’ IEEE Trans. , Vol. 39, No. 7, July 1991, pp. 1046–1048. , H. T. Nicholas, and H. Samueli, ‘‘The Optimization of Direct Digital Frequency Synthesizer in the Presence of Finite Word Length Effects,’’ Proc. , Baltimore, MD, 1988, pp.