Download Clock Generators for SOC Processors: Circuits and by Amr Fahim PDF
By Amr Fahim
This ebook examines the problem of layout of fully-integrated frequency synthesizers appropriate for system-on-a-chip (SOC) processors. This booklet takes a extra international layout standpoint in together reading the layout area on the circuit point in addition to on the architectural point. The insurance of the e-book is entire and comprises precis chapters on circuit idea in addition to suggestions keep watch over idea appropriate to the operation of part locked loops (PLLs). at the circuit point, the dialogue contains low-voltage analog layout in deep submicron electronic CMOS procedures, results of offer noise, substrate noise, in addition machine noise. at the architectural point, the dialogue contains PLL research utilizing continuous-time in addition to discrete-time types, linear and nonlinear results of PLL functionality, and specific research of locking habit.
The fabric then develops into precise circuit and architectural research of particular clock new release blocks. This contains circuits and architectures of PLLs with excessive energy offer noise immunity and electronic PLL architectures the place the loop filter out is digitized.
Methods of producing low-spurious sampling clocks for discrete-time analog blocks are then tested. This contains sigma-delta fractional-N PLLs, Direct electronic Synthesis (DDS) thoughts and non-conventional makes use of of PLLs. layout for try (DFT) concerns as they come up in PLLs are then mentioned. This comprises equipment of correctly measuring jitter and built-in-self-test (BIST) recommendations for PLLs. eventually, clocking concerns as a rule linked to system-on-a-chip (SOC) designs, reminiscent of a number of clock area interfacing and partitioning, and exact clock section iteration recommendations utilizing delay-locked loops (DLLs) also are addressed. The booklet offers a variety of actual global functions, in addition to useful rules-of-thumb for contemporary designers to take advantage of on the method, architectural, in addition to the circuit point. This publication is definitely suited to practitioners in addition to graduate point scholars who desire to study extra approximately time-domain research and layout of frequency synthesis techniques.
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Additional info for Clock Generators for SOC Processors: Circuits and Architectures
For this reason, a is usually designed to be 2 to 3 to cover process and temperature variation. Another requirement is that the gain of the V2I converter be linear with the input voltage (for quadratic variation in current). 43) To obtain a required gain, the size of pN may be relatively large. This means that pp must also be large. For large gain requirements, the poles introduced by the PMOS current mirrors may start to approach the closed loop bandwidth of the PLL and alter the PLL dynamics.
However, when larger supply voltages are used, this technique does not offer much of an advantage over the previous V2I topology in terms of increasing the VFiLT,max In both V2I topologies discussed above, the filter voltage is limited on the low side by VTN- An alternative method of recovering voltage headroom is to use a rail-to-rail V2I converter . This V2I converter has two input stages. One is a NMOS input stage that works from VDD/2 to VDD- The other is a PMOS input stage that works from OV to VDD/2.
There are several methods of designing ring oscillators. Two general methods are considered here: single-ended and differential ring oscillators. A generic single-ended ring oscillator is shown in Figure 3-23. In this case, a 3-stage ring oscillator is shown and the delay stages are simply CMOS inverters. A single current source is used for all 3, Low-Voltage Analog CMOS Design 49 three delay stages. This is done in order to prevent the current source from turning on and off and thus disrupting the value of the current being supplied (as was shown in the case of a single-ended charge pump shown in Figure 312).